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SCN2681T Dual asynchronous receiver/transmitter (DUART)
Product specification Supersedes data of 1995 May 01 IC19 Data Handbook 1998 Sep 04
Philips Semiconductors
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
DESCRIPTION
The Philips Semiconductors SCN2681 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip MOS-LSI communications device that provides two independent full-duplex asynchronous receiver/transmitter channels in a single package. The SCN2681T features a faster bus cycle time than the standard SCN2681. The quick bus cycle eliminates or reduces the need for wait states with fast CPUs and permits high throughput in I/O intensive systems. Higher external clock rates may be used with the transmitter, receiver and counter timer which in turn provide greater versatility in baud rate generation. The SCN2681T interfaces directly with microprocessors and may be used in a polled or interrupt driven system. The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of eighteen fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems. Each receiver is quadruple buffered to minimize the potential of receiver over-run or to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided to disable a remote DUART transmitter when the receiver buffer is full. Also provided on the SCN2681T are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. For a complete functional description and programming information for the SCN2681T, refer to the SCN2681 product specification.
* Programmable baud rate for each receiver and transmitter
selectable from: - 22 fixed rates: 50 to 115.2k baud - Non-standard rates to 115.2 - Non-standard user-defined rate derived from programmable counter/timer - External 1X or 16X clock
* Parity, framing, and overrun error detection * False start bit detection * Line break detection and generation * Programmable channel mode
- Normal (full-duplex) - Automatic echo - Local loopback - Remote loopback
* Multi-function programmable 16-bit counter/timer * Multi-function 7-bit input port
- Can serve as clock or control inputs - Change of state detection on four inputs - 100k typical pull-up resistors
* Multi-function 8-bit output port
- Individual bit set/reset capability - Outputs can be programmed to be status/interrupt signals
* Versatile interrupt system
- Single interrupt output with eight maskable interrupting conditions - Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
FEATURES
* Maximum data transfer rates:
1X - 1MB/sec transmitter and receiver; 16X - 500kB/sec receiver and 250kB/sec transmitter
* Fast bus cycle times reduce or eliminate CPU wait states * Dual full-duplex asynchronous receiver/transmitters * Quadruple buffered receiver data registers * Programmable data format
- 5 to 8 data bits plus parity - Odd, even, no parity or force parity - 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
* 16-bit programmable Counter/Timer
ORDERING INFORMATION
DESCRIPTION 40-Pin Plastic Dual In-Line Package (600mil-wide DIP)
* Automatic wake-up mode for multidrop applications * Start-end break interrupt/status * Detects break which originates in the middle of a character * On-chip crystal oscillator * Single +5V power supply * Commercial and industrial temperature ranges available
VCC = +5V +10%, TA = 0C to +70C SCN2681TC1N40 SCN2681TC1A44
DWG # SOT129-1 SOT187-2
44-Pin Plastic Lead Chip Carrier (PLCC) NOTE: For a full register description and programming information see the SCN2681.
1998 Sep 04
2
853-1002 19970
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PIN CONFIGURATIONS
INDEX CORNER A0 IP3 A1 IP1 A2 A3 IP0 WRN 1 2 3 4 5 6 7 8 40 VCC 39 IP4 38 IP5 37 IP6 36 IP2 35 CEN 34 RESET 33 X2 32 X1/CLK 31 RxDA DIP TxDB 11 OP1 12 OP3 13 30 TxDA 29 OP0 28 OP2 27 OP4 26 OP6 25 D0 24 D2 23 D4 22 D6 21 INTRN 17 18 TOP VIEW PIN/FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC A0 IP3 A1 IP1 A2 A3 IP0 WRN RDN RxDB NC TxDB OP1 OP3 OP5 OP7 D1 D3 D5 D7 GND PIN/FUNCTION 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC INTRN D6 D4 D2 D0 OP6 OP4 OP2 OP0 TxDA NC RxDA X1/CLK X2 RESET CEN IP2 IP6 IP5 IP4 VCC 28 29 PLCC 7
6
1
40 39
RDN 9 RxDB 10
OP5 14 OP7 15 D1 16 D3 17 D5 18 D7 19 GND 20
SD00098
Figure 1. Pin Configurations NOTE: Refer to SCN2681 for functional description.
1998 Sep 04
3
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
BLOCK DIAGRAM
8 D0-D7 BUS BUFFER
CHANNEL A TRANSMIT HOLDING REG TRANSMIT SHIFT REGISTER TxDA
RDN WRN CEN A0-A3 RESET 4
OPERATION CONTROL ADDRESS DECODE R/W CONTROL RECEIVE HOLDING REG (3) RxDA RECEIVE SHIFT REGISTER MRA1, 2 CRA SRA
INTERRUPT CONTROL INTRN IMR ISR CHANNEL B (AS ABOVE) TxDB RxDB INTERNAL DATABUS
INPUT PORT CHANGE OF STATE DETECTORS (4) IPCR ACR
CONTROL
TIMING BAUD RATE GENERATOR
TIMING
7
IP0-IP6
CLOCK SELECTORS
COUNTER/ TIMER
OUTPUT PORT FUNCTION SELECT LOGIC 8
X1/CLK XTAL OSC X2 CSRA CSRB ACR U CTLR CTLR
OP0-OP7
OPCR OPR
VCC GND
SD00099
Figure 2. Block Diagram
1998 Sep 04
4
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PIN DESCRIPTION
MNEMONIC D0-D7 CEN TYPE I/O I NAME AND FUNCTION Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and the CPU. D0 is the least significant bit. Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN, and A0-A3 inputs. When CEN is high, the DUART places the D0-D7 lines in the three-state condition. Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. Address Inputs: Select the DUART internal registers and ports for read/write operations. Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in the high state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (high) state. Clears Test modes, sets MR pointer to MR1. Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable interrupting conditions are true. Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing. Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it is permissible to ground it. Channel A Receiver Serial Data Input: The least significant bit is received first. `Mark' is high, `space' is low. Channel B Receiver Serial Data Input: The least significant bit is received first. `Mark' is high, `space' is low. Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. `Mark' is high, `space' is low. Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. `Mark' is high, `space' is low. Output 0: General purpose output, or channel A request to send (RTSAN, active-low). Can be deactivated automatically on receive or transmit. Output 1: General purpose output, or channel B request to send (RTSBN, active-low). Can be deactivated automatically on receive or transmit. Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output. Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter 1X clock output, or channel B receiver 1X clock output. Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFULLA output. Output 5: General purpose output, or channel B open-drain, active-low, RxRDYB/FFULLB output. Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output. Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output. Input 0: General purpose input, or channel A clear to send active-low input (CTSAN). Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Input 1: General purpose input, or channel B clear to send active-low input (CTSBN). Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Input 2: General purpose input, or counter/timer external clock input. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device supplying 1 to 4 mA of current. Power Supply: +5V supply input. Ground
WRN RDN A0-A3 RESET
I I I I
INTRN X1/CLK X2 RxDA RxDB TxDA TxDB
O I I I I O O
OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 IP0 IP1 IP2 IP3
O O O O O O O O I I I I
IP4
I
IP5
I
IP6
I
VCC GND
I I
1998 Sep 04
5
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG PARAMETER Operating ambient temperature range2 Storage temperature range All voltages with respect to GND3 RATING 0 to +70 -65 to +150 -0.5 to +6.0 UNIT C C
V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
DC ELECTRICAL CHARACTERISTICS1, 2, 3
SYMBOL VIL VIH VIH VOL VOH IIL ILL IX1L IX1H IX2L IX2H IOC PARAMETER Input low voltage Input high voltage (except X1/CLK) Input high voltage (X1/CLK) Output low voltage Output high voltage (except o.c. outputs)4 Input leakage current Data bus 3-state leakage current X1/CLK low input current X1/CLK high input current X2 low input current X2 high input current Open-collector output leakage current IOL = 2.4mA IOH = -400A VIN = 0 to VCC VO = 0.4 to VCC VIN = 0, X2 grounded VIN = 0, X2 floated VIN = VCC, X2 = grounded VIN = VCC, X2 floated VIN = 0, X1/CLK floated VIN = VCC, X1/CLK floated VO = 0.4 to VCC TEST CONDITIONS LIMITS Min 2.0 3.5 0.4 2.4 -10 -10 -4 -3 -1 0 -100 0 -10 -2 -1.5 0.2 3.5 -30 +30 10 10 0 0 1 10 0 100 10 Typ Max 0.8 V UNIT
V A mA mA mA mA A A A
ICC Power supply current5 150 mA NOTES: 1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC supply range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 3. Typical values are at +25C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7k to VCC. 5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
RESET tRES
SD00028
Figure 3. Reset Timing NOTES: 1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and VCC supply range. 2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 3. Typical values are at +25C, typical supply voltages, and typical processing parameters. 4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7k to VCC.
1998 Sep 04
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Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
SYMBOL tRES Reset pulse width
PARAMETER
LIMITS Min 1.0 Max
UNIT s
A0-A3
tAVEL
tELAX
CEN (READ) tEHEL tRLRH
RDN tRLDV tRLDA D0-D7 (READ) FLOAT INVALID VALID
tRHDF tRHDI
FLOAT
CEN (WRITE) tEHEL tWLWH WRN
tDVWH tWHDI D0-D7 (WRITE) VALID
SD00100
Figure 4. Bus Timing LIMITS Min Max
SYMBOL
PARAMETER1
UNIT
tAVEL A0-A3 setup to RDN and CEN, or WRN and CEN low 0 ns tELAX RDN and CEN, or WRN and CEN low to A0-A3 invalid 100 ns tRLRH RDN and CEN low to RDN or CEN high 120 ns tEHEL CEN high to CEN low2, 3 110 ns tRLDA CEN and RDN low to data outputs active 15 ns tRLDV CEN and RDN low to data valid 100 ns tRHDI CEN or RDN high to data invalid 10 ns tRHDF CEN or RDN high to data outputs floating 65 ns tWLWH WRN and CEN low to WRN or CEN high 75 ns tDVWH Data input valid to WRN or CEN high 35 ns tWHDI WRN or CEN high to data invalid 15 ns NOTES: 1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 2. If CEN is used as the `strobing' input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must be negated for tEHEL to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the RDN input even if the CEN is used as the strobing signal for bus operations. 3. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes. 1998 Sep 04 7
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
RDN tPS IP0-IP6 tPH
(a) INPUT PINS WRN tPD
OP0-OP7
OLD DATA NEW DATA (b) OUTPUT PINS
SD00101
Figure 5. Port Timing
SYMBOL tPS tPH tPD
PARAMETER1 Port input setup time before RDN low Port input hold time after RDN high Port output valid after WRN high
LIMITS Min 0 0 200 Max
UNIT ns ns ns
NOTE: 1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.
WRN
VM
tIR INTERRUPT 1 OUTPUT VOL +0.5V VOL NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal, VM, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and test environment are pronounced and can greatly affect the resultant measurement. SD00102
Figure 6. Interrupt Timing LIMITS Min INTRN (or OP3-OP7 when used as interrupts) negated from: Read RHR (RxRDY/FFULL interrupt) Write THR (TxRDY interrupt) Reset command (delta break interrupt) Stop C/T command (counter interrupt) Read IPCR (input port change interrupt) Write IMR (clear of interrupt mask bit) Max 200 200 200 200 200 200 ns ns ns ns ns ns
SYMBOL
PARAMETER
UNIT
tIR
1998 Sep 04
8
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
R1: 100K - 1Meg (See design note) C1 = C2: 0-5pF + (STRAY < 5pF) tCLK tCTC tRx tTx 1K DRIVING FROM EXTERNAL SOURCE 74LS04
+5V
X1/CLK CTCLK RxC TxC
CLOCK TO OTHER CHIPS
SCN2681 X1 tCLK tCTC tRx tTx OPEN +5V R1 1K X1 C1 R2 TO THE REST OF THE DUART CIRCUITS
When using an external clock it is preferred to drive X2 and leave X1 open. X2 is the input to the internal driver, while X1 is the output. R1 is only required if U1 will not drive to X2 high level. Previous specifications indicated X2 should be grounded and X1 should be driven. This is still acceptable. It is electrically easier to drive the amplifier input than to overdrive its output.
C2 X2 X2 3.6864MHz CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180 R2 = 50k to 150k
U1
SD00091
Figure 7. Clock Timing LIMITS Min 90 2 55 0 55 0 0 110 0 0 Typ Max 4 8 3.6864 8 1 4 1
SYMBOL
PARAMETER X1/CLK high or low time X1/CLK frequency CTCLK (IP2) high or low time CTCLK (IP2) frequency1 RxC high or low time RxC frequency (16X)1 (1X)1 TxC high or low time TxC frequency (16X)1 (1X)1
UNIT ns MHz ns MHz ns MHz MHz ns MHz MHz
tCLK fCLK tCTC fCTC tRX fRX tTX fTX
NOTE: 1. Minimum frequencies are not tested but are guaranteed by design.
1 BIT TIME (1 OR 16 CLOCKS)
TxC (INPUT) tTXD TxD
tTCS TxC (1X OUTPUT)
SD00103
Figure 8. Transmit LIMITS Min tTXD tTCS TxD output delay from TxC external clock input on IP pin Output delay from TxC low at OP pin to TxD data output 0 Max 300 100 ns ns
SYMBOL
PARAMETER
UNIT
1998 Sep 04
9
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
RxC (1X INPUT)
tRXS RxD
tRXH
SD00104
Figure 9. Receive LIMITS Min tRXS tRXH RxD data setup time before RxC high at external clock input on IP pin RxD data hold time after RxC high at external clock input on IP pin 200 25 Max ns ns
SYMBOL
PARAMETER
UNIT
TxD TRANSMITTER ENABLED TxRDY (SR2)
D1
D2
D3
BREAK
D4
D6
WRN D1 CTSN1 (IP0) D2 D3 START BREAK D4 STOP BREAK D5 WILL NOT BE TRANSMITTED D6
RTSN2 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR2(4) = 1. 2. Timing shown for MR2(5) = 1. OPR(0) = 1
SD00094
Figure 10. Transmitter Timing
1998 Sep 04
10
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
RxD
D1
D2
D3
D4
D5
D6
D7
D8
D6, D7, D8 WILL BE LOST RECEIVER ENABLED
RxRDY (SR0)
FFULL (SR1)
RxRDY/ FFULL (OP5)2
RDN S D D1 OVERRUN (SR4)
S = STATUS D = DATA
S
D D2
SD D3
SD D4 RESET BY COMMAND
D5 WILL BE LOST
RTS1 (OP0) OPR(0) = 1 NOTES: 1. Timing shown for MR1(7) = 1. 2. Shown for OPCR(4) = 1 and MR1(6) = 0.
SD00105
Figure 11. Receiver Timing
MASTER STATION TxD
BIT 9 ADD#1 1 D0
BIT 9 0
BIT 9 ADD#2 1
TRANSMITTER ENABLED TxRDY (SR2)
WRN MR1(4-3) = 11 MR1(2) = 1 ADD#1 MR1(2) = 0 D0 MR1(2) = 1 ADD#2
PERIPHERAL STATION BIT 9 RxD RECEIVER ENABLED 0 BIT 9 ADD#1 1 D0 BIT 9 0 BIT 9 ADD#2 1 BIT 9 0
RxRDY (SR0)
RDN/WRN MR1(4-3) = 11 ADD#1
S D0
D
S = STATUS D = DATA
S
D ADD#2
SD00106
Figure 12. Wake-Up Mode 1998 Sep 04 11
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1998 Sep 04
12
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1998 Sep 04
13
Philips Semiconductors
Product specification
Dual asynchronous receiver/transmitter (DUART)
SCN2681T
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 09-98 Document order number: 9397 750 04363
Philips Semiconductors
1998 Sep 04 14

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